One of the major bottlenecks that limit parallelization of code in microprocessors is dependency between memory-access instructions. Various techniques have been proposed to improve parallelization performance of code that includes memory access. For example, Tyson and Austin propose a technique referred to as “memory renaming,” in “Memory Renaming: Fast, Early and Accurate Processing of Memory Communication,” International Journal of Parallel Programming, Volume 27, No. 5, 1999, which is incorporated herein by reference. Memory renaming is a modification of the processor pipeline that applies register access techniques to load and store instructions to speed the processing of memory traffic. The approach works by predicting memory communication early in the pipeline, and then re-mapping the communication to fast physical registers.